When a large panel display such as a large liquid crystal display (LCD) is viewed at a wide angle, the color of the displayed image may not be clearly viewed because of light scattering. One method of dealing with such light scattering is the 2-TFT (thin film transistor) method for the LCD.
FIG. 1 shows a 2-TFT pixel 100 including a first sub-pixel 102 and a second sub-pixel 104. The first sub-pixel 102 includes a first TFT (thin film transistor) MNA having a drain coupled to a first sub-pixel electrode represented as a first storage capacitor Cst-a and a first liquid crystal capacitor Clc-a coupled between the first storage capacitor Cst-a and a ground node. The second sub-pixel 104 includes a second TFT (thin film transistor) MNB having a drain coupled to a second sub-pixel electrode represented as a second storage capacitor Cst-b and a second liquid crystal capacitor Clc-b coupled between the second storage capacitor Cst-b and the ground node.
The first and second storage capacitors Cst-a and Cst-b are coupled to each other at a coupling node Cst. The first TFT MNA has a gate coupled to a first gate line Gate-a, and the second TFT MNB has a gate coupled to a second gate line Gate-b. The first and second TFT's MNA and MNB have sources coupled to a source line 106.
For displaying gray scale data at the pixel 100, a respective voltage ΔV is desired to be biased across each of the storage capacitors Cst-a and Cst-b and each of the liquid crystal capacitors Clc-a and Clc-b, in accordance to the luminance curves of FIG. 2. Referring to FIG. 2, for any given gray scale data to be displayed at the pixel 100, a first respective voltage ΔV1 for that gray scale data is desired to be biased across the first storage and liquid crystal capacitors Cst-a and Clc-a, and a lower second respective voltage ΔV2 for that gray scale data is desired to be biased across the second storage and liquid crystal capacitors Cst-b and Clc-b.
During operation of the pixel 100, the first gate line Gate-a is activated to turn on the first TFT MNA (while the second TFT MNB is turned off) to bias the first storage and liquid crystal capacitors Cst-a and Clc-a with the first respective voltage ΔV1 at the source line 106 while the coupling node Cst is biased to a VCOM voltage (i.e., a voltage at a common electrode of the display panel having the pixel 100). Thereafter, the second gate line Gate-b is activated to turn on the second TFT MNB (while the first TFT MNA is turned off) to bias the second storage and liquid crystal capacitors Cst-b and Clc-b with the second respective voltage ΔV2 at the source line 106 while the coupling node Cst is biased to the VCOM voltage.
With such different biases, the first sub-pixel 102 exhibits a first luminance, and the second sub-pixel 104 exhibits a second luminance that is different from the first luminance. Referring to FIG. 2, the pixel 100 exhibits an average luminance that is an average of the first and second luminances from the first and second pixels 102 and 104, in accordance with the average luminance curve 108 (shown as a dashed line in FIG. 2).
In the prior art 2-TFT method, two voltages ΔV1 and ΔV2 are independently transferred from a timing controller to a source driver for driving the source line 106 with the two voltages ΔV1 and ΔV2 during one line time period for driving the multiple sub-pixels 102 and 104. Thus, the data transfer rate and/or the number of data buses are increased by two times which disadvantageously in turn increases power consumption and EMI (electromagnetic interference).
Thus, a mechanism is desired for driving the multiple sub-pixels 102 and 104 of the pixel 100 with minimized data transfer rate and/or number of data buses.